1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2009, zarlink semiconductor inc. all rights reserved. features ? can be used in systems to support the requirements of itu-t g.8262 for synchronous ethernet equipment slave clocks (eec option 1 and 2) ? meets jitter generation requirements of telcordia gr-253-core for oc-192, oc-48, oc-12 and oc-3 rates ? meets jitter generation requirements of itu-t g.813 for stm-64, stm-16, stm-4 and stm-1 rates ? synchronizes to standard telecom or ethernet clock and provides jitter filtered output clock for sonet/sdh and synchronous ethernet line cards ? synchronizes to telecom reference clocks (2 khz, n*8 khz up to 77.76 mhz, 155.52 mhz) or to ethernet reference clocks (25 mhz, 50 mhz, 62.5 mhz, 125 mhz) ? generates standard sonet/sdh clock rates (e.g., 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, 622.08 mhz) or ethernet clock rates (e.g., 25 mhz, 50 mhz, 125 mhz, 156.25 mhz, 312.5 mhz) for synchronizing ethernet phys ? selectable loop bandwidth of 14 hz, 28 hz, or 890 hz ? configurable through a serial interface (spi or i 2 c) ? dpll can be configured to provide synchronous or asynchronous clock outputs ? supports ieee 1149.1 jtag boundary scan applications ? itu-t g.8262 line cards which support 1 gbe and 10 gbe interfaces ? sonet line cards up to oc-192 ? sdh line cards up to stm-64 february 2009 figure 1 - simplified functional block diagram apll_clk ref diff sonet/sdh/ ethernet apll dpll ref /n i 2 c/spi jtag osco osci lock hold ZL30145 synce (10 gbe) sonet/sdh rate conversion and jitter attenuator pll short form data sheet ordering information ZL30145ggg 64 pin cabga trays ZL30145ggg2 64 pin cabga* trays *pb free tin/silver/copper -40 o c to +85 o c
ZL30145 short form data sheet 2 zarlink semiconductor inc. 1.0 high level overview the ZL30145 is a highly integrated device that provides timing for line cards. the dpll automatically locks to one input reference and provides two sy nchronized output clocks for sync hronizing sonet/sdh and synchronous ethernet line cards. the ZL30145 has a on-chip digital phase-locked loop (d pll) designed to provide rate conversion and jitter attenuation for synchronous ethernet, (synce), synchr onous digital hierarchy (sdh) and synchronous optical network (sonet) networking equipment. the ZL30145 generat es very low jitter clocks that meet the jitter requirements of itu-t g.8262, telcor dia gr-253-core oc-48, oc-12, oc-3 , oc-1 rates and itu-t g.813 stm- 16, stm-4 and stm-1 rates.
c zarlink semiconductor 2005 all rights reserved. issue apprd. date acn package code previous package codes
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of prod uct or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any pu rpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to pe rform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl, the zarlink semiconductor logo and the legerity logo and combinations thereof, voiceedge, voiceport, slac, islic, islac and voicepath are trademarks of zarlink semiconductor inc. technical documentation - not for resale for more information ab out all zarlink products visit our web site at
|
